1. Technical Field
The present invention relates to wireless radio systems and, more particularly, phase locked loops for use in radio front end circuitry.
2. Related Art
The demand for high performance universal frequency synthesizers is growing with the increasing performance and integration requirements of wireless radio frequency (RF) systems, such as cellular telephony and FM radio systems. Phase locked loop (PLL) frequency synthesis is a popular indirect frequency synthesis method for high performance applications due to its agility and the ability of synthesizing frequencies over wide bandwidths with narrow channel spacing. However, PLL synthesizer design still remains a challenging aspect of RF system design, because of the stringent requirements typically imposed on frequency synthesizers. For example, frequency synthesizers are typically required to be defined with an output frequency accuracy on the order of a few parts per million (PPM). Furthermore, in most cases, the output frequency must also be capable of being varied in small precise steps, such as a few hundred kilo-hertz (kHz), corresponding to the RF channel spacing.
There are two predominant types of PLL frequency synthesizers, type 1 PLL's and type 2 PLL's. Type 1 PLL's typically include a precise crystal oscillator (X-TAL) providing a reference signal, a phase detector for producing an error signal indicative of a difference in phase between the reference signal and a feedback signal, a sample/reset lowpass loop filter (LPF) for filtering the error signal to produce a control voltage, a voltage controlled oscillator for producing an oscillation based on the control voltage and one or more divider blocks in the feedback path that each divide the incoming signal by some integer of either fixed or on-the-fly programmable value to produce the feedback signal. Type 2 PLL's differ from type 1 PLL's in that instead of a phase detector, type 2 PLL's typically include a phase frequency detector (PFD) for detecting a difference in phase or frequency between the reference signal and the feedback signal and a charge pump (CP) that generates a current pulse proportional to the difference in phase or frequency.
The combination of the PFD and charge pump enables type 2 PLL's to locking a wider range of frequencies than type 1 PLL's. As such, type 2 PLL's are often used in analog and RF circuit designs. However, the system stability in type 2 PLL's is more difficult to manage than in type 1 PLL's. Therefore, type 2 PLL's typically require a double pole (second order) LPF to provide a narrow LPF bandwidth, while type 1 PLL's typically only need a single pole LPF. Double pole LPF's require larger capacitors than single pole LPF's. Therefore, the size of type 2 PLL's is usually much larger than the size of type 1 PLL's. For example, with a reference clock of 5 MHz, a type 2 PLL may require up to a 500 pF capacitor, while a type 1 PLL would need at most a 70 pF capacitor. However, the frequency locking range of the type 1 PLL would be only 143 MHz due to the phase detector operation limit, as compared to an approximately infinite frequency locking range of the type 2 PLL.
Therefore, a need exists for a PLL design with minimal size that provides a substantially infinite frequency locking range.